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RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor.

, , , , , , , , , and . ISORC, page 193-201. IEEE Computer Society, (2010)

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Exploiting Intel TSX for fault-tolerant execution in safety-critical systems., , , and . DFT, page 197-202. IEEE Computer Society, (2014)Analysable instruction memories for hard real-time systems.. University of Augsburg, (2012)A comparison of instruction memories from the WCET perspective., and . Journal of Systems Architecture - Embedded Systems Design, 60 (5): 452-466 (2014)RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor., , , , , , , , , and . ISORC, page 193-201. IEEE Computer Society, (2010)RTOS support for execution of parallelized hard real-time tasks on the MERASA multi-core processor., , , , , , , , , and . Comput. Syst. Sci. Eng., (2011)Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate., and . HPCC-ICESS, page 1442-1449. IEEE Computer Society, (2012)A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware., , , and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 122-134. Springer, (2011)Predictable dynamic instruction scratchpad for simultaneous multithreaded processors., , , and . MEDEA@PACT, page 38-45. ACM, (2008)Replacement Policies for a Function-Based Instruction Memory: A Quantification of the Impact on Hardware Complexity and WCET Estimates., and . ECRTS, page 112-121. IEEE Computer Society, (2012)A hard real-time capable multi-core SMT processor., , , , , , , and . ACM Trans. Embedded Comput. Syst., 12 (3): 79:1-79:26 (2013)