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Disambiguation of "Jacob, Philip"

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Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers.

, , , , , , , , , , , and . 3DIC, page 1-7. IEEE, (2009)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Martine Jacob University of Stuttgart

Philip Dörge University of Stuttgart

Philip Russ University of Stuttgart

Univ. -Prof. Dr. -Ing. Philip Leistner University of Stuttgart

Philip Reitinger University of Stuttgart

 

Other publications of authors with the same name

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU., , , , , , , , , and . IEEE Access, (2015)Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking., , , , , , , , and . ICCD, page 202-207. IEEE, (2007)Viper - A 3D-Modeling and Visualization Toolkit for Web-Based Applications., , and . Computer Networks, 30 (1-7): 626-628 (1998)Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers., , , , , , , , , and 2 other author(s). 3DIC, page 1-7. IEEE, (2009)An Improved Shading Algorithm for Radiosity Based Renderers.. Focus on Scientific Visualization, page 317-324. Springer, (1991)Raytracing mit BSP-Volumen - ein globales, physikalisch-basiertes Beleuchtungsmodell.. Universität Kaiserslautern, (1995)Empirical Validation of the Performance of a Class of Transient Detector., and . Evolutionary Computing, AISB Workshop, volume 1305 of Lecture Notes in Computer Science, page 129-146. Springer, (1997)A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology., , , , , and . J. Solid-State Circuits, 45 (2): 380-390 (2010)Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications., , , , , and . IET Circuits, Devices & Systems, 5 (3): 159-169 (2011)A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration., , , , , and . IEEE Trans. VLSI Syst., 18 (6): 967-977 (2010)