PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Gupta, Subhanshu"

Author of the publication

copydeleteadd this publication to your clipboard
Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch.

, , , , and . IEEE Trans. on Circuits and Systems, 55-I (3): 817-827 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shriya Gupta University of Stuttgart

Ratnesh Kumar Gupta University of Stuttgart

 

Other publications of authors with the same name

Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems., , , , and . ICASSP, page 1585-1588. IEEE, (2011)A Hybrid ΔΣ/Nyquist Rate Switched Capacitor Power Amplifier in 65nm CMOS., , , , and . MWSCAS, page 290-293. IEEE, (2018)A Mode-I/Mode-III UWB LNA with programmable gain and 20 dB WLAN blocker rejection in 130nm CMOS., , and . ISCAS, page 1093-1096. IEEE, (2010)Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators., , , and . ISCAS, page 2414-2417. IEEE, (2008)A 0.22-μW Single-Bit VCO-Based Time-Domain Sensor-to-Digital Front-End With Reduced Supply Sensitivity., and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (1): 148-159 (2022)Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch., , , , and . IEEE Trans. on Circuits and Systems, 55-I (3): 817-827 (2008)Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs., , , and . Signal Processing Systems, 69 (3): 329-338 (2012)Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A., , , and . IEEE Trans. on Circuits and Systems, 64-I (1): 3-13 (2017)Design considerations for a 10 GHz CMOS transmit-receive switch., , and . ISCAS (3), page 2104-2107. IEEE, (2005)A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS., , , , and . J. Solid-State Circuits, 47 (5): 1141-1153 (2012)