Author of the publication

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1.

, , , , , and . IEEE Trans. on Circuits and Systems, 60-I (11): 2834-2844 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation., , , , and . APCCAS, page 128-131. IEEE, (2012)A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time., , and . CICC, page 1-4. IEEE, (2019)TSA-Net: Tube Self-Attention Network for Action Quality Assessment., , , , and . CoRR, (2022)A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method., , , , and . ASICON, page 1-4. IEEE, (2015)Exploring the programmability for deep learning processors: from architecture to tensorization., , , , and . DAC, page 15:1-15:6. ACM, (2018)Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR., , , , , and . ESSCIRC, page 189-192. IEEE, (2019)An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators., , , , and . IEEE Trans. on Circuits and Systems, 62-II (8): 721-725 (2015)iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (2): 346-357 (2019)OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 519-530 (2018)A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application., , , , , , , and . ASICON, page 492-495. IEEE, (2011)