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Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.

B. Mao, W. Hu, A. Althoff, J. Matai, Y. Tai, D. Mu, T. Sherwood, and R. Kastner. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (9): 1719-1732 (2018)

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Hiding Intermittent Information Leakage with Architectural Support for Blinking.A. Althoff, J. McMahan, L. Gutierrez, S. Davidson, T. Sherwood, M. Taylor, and R. Kastner. ISCA, page 638-649. IEEE Computer Society, (2018)Synthesizable Higher-Order Functions for C++.D. Richmond, A. Althoff, and R. Kastner. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (11): 2835-2844 (2018)Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs.P. Meng, A. Althoff, Q. Gautier, and R. Kastner. DATE, page 918-923. IEEE, (2016)Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.B. Mao, W. Hu, A. Althoff, J. Matai, Y. Tai, D. Mu, T. Sherwood, and R. Kastner. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (9): 1719-1732 (2018)Quantifying hardware security using joint information flow analysis.R. Kastner, W. Hu, and A. Althoff. DATE, page 1523-1528. IEEE, (2016)Benchmarking Video with the Surgical Image Registration Generator (SIRGn) Baseline.M. Barrow, N. Ho, A. Althoff, P. Tueller, and R. Kastner. ISVC (2), volume 11845 of Lecture Notes in Computer Science, page 320-331. Springer, (2019)Composable, parameterizable templates for high-level synthesis.J. Matai, D. Lee, A. Althoff, and R. Kastner. DATE, page 744-749. IEEE, (2016)An Architecture for Learning Stream Distributions with Application to RNG Testing.A. Althoff, and R. Kastner. DAC, page 15:1-15:6. ACM, (2017)FPGA Architectures for Real-time Dense SLAM.Q. Gautier, A. Althoff, and R. Kastner. ASAP, page 83-90. IEEE, (2019)Towards Property Driven Hardware Security.W. Hu, A. Althoff, A. Ardeshiricham, and R. Kastner. MTV, page 51-56. IEEE Computer Society, (2016)

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Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.

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Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.