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Multicore Resource Management., , , , , and . IEEE Micro, 28 (3): 6-16 (2008)QoS for High-Performance SMT Processors in Embedded Systems., , , , , and . IEEE Micro, 24 (4): 24-31 (2004)Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns., , and . ISORC, page 142-149. IEEE Computer Society, (2016)SMT Malleability in IBM POWER5 and POWER6 Processors., , , , , , , and . IEEE Trans. Computers, 62 (4): 813-826 (2013)Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors., , , , , , and . ISORC, page 208-217. IEEE Computer Society, (2015)Design and integration of hierarchical-placement multi-level caches for real-time systems., , , and . DATE, page 455-460. IEEE, (2018)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)Software Time Reliability in the Presence of Cache Memories., , , , , , and . Ada-Europe, volume 10300 of Lecture Notes in Computer Science, page 233-249. Springer, (2017)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems., , , , and . RTAS, page 267-278. IEEE Computer Society, (2016)