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Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (5): 808-821 (2015)

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Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing., and . IEEE Trans. VLSI Syst., 22 (3): 516-521 (2014)Timing attack on NEMS relay based design of AES., , , and . VLSI-SoC, page 264-269. IEEE, (2015)Expedited response compaction for scan power reduction., and . VTS, page 40-45. IEEE Computer Society, (2011)Test-mode-only scan attack and countermeasure for contemporary scan architectures., , , and . ITC, page 1-8. IEEE Computer Society, (2014)DfT support for launch and capture power reduction in launch-off-capture testing., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Activation of logic encrypted chips: Pre-test or post-test?, , , and . DATE, page 139-144. IEEE, (2016)Slack removal for enhanced reliability and trust., , and . DTIS, page 1-4. IEEE, (2014)CAD-Base: An Attack Vector into the Electronics Supply Chain., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 38:1-38:30 (2019)Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 15 (3): 23:1-23:17 (2019)Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation., and . CoRR, (2022)