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Virtual Power Management simulation framework for computer systems., , , , and . ISPASS, page 128-129. IEEE Computer Society, (2013)Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors., , and . IEEE Trans. VLSI Syst., 14 (9): 1039-1043 (2006)Exploiting compiler-generated schedules for energy savings in high-performance processors., , and . ISLPED, page 414-419. ACM, (2003)What Computer Architects Need to Know about Memory Throttling., and . ISCA Workshops, volume 6161 of Lecture Notes in Computer Science, page 233-242. Springer, (2010)On-Chip Interconnection Networks of the TRIPS Chip., , , , , , and . IEEE Micro, 27 (5): 41-50 (2007)Implementation and Evaluation of a Dynamically Routed Processor Operand Network., , , , , , and . NOCS, page 7-17. IEEE Computer Society, (2007)Application-Aware Power Management., , , , and . IISWC, page 39-48. IEEE Computer Society, (2006)Static Energy Reduction Techniques for Microprocessor Caches., , , , and . ICCD, page 276-283. IEEE Computer Society, (2001)Distributed Microarchitectural Protocols in the TRIPS Prototype Processor., , , , , , , , , and 7 other author(s). MICRO, page 480-491. IEEE Computer Society, (2006)Microprocessor pipeline energy analysis., , , , and . ISLPED, page 282-287. ACM, (2003)