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Design and Analysis of a Class-D Stage With Harmonic Suppression., , and . IEEE Trans. on Circuits and Systems, 59-I (6): 1178-1186 (2012)A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS., , , and . ISSCC, page 424-613. IEEE, (2007)Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract)., , , and . VLSI Design, page 16-17. IEEE Computer Society, (2002)Envelope detector sensitivity and blocking characteristics., and . ECCTD, page 773-776. IEEE, (2011)Self-Synchronized Vector Transfer for High Speed Parallel Systems., and . ICPADS, page 2-9. IEEE Computer Society, (1998)Efficient High-Speed CMOS Design by Layout Based Schematic Method., and . EUROMICRO, page 10337-10340. IEEE Computer Society, (1998)Modeling of dynamic errors in algorithmic A/D converters., , and . ISCAS (5), page 455-458. IEEE, (2001)Application of Knowledge-based System in a B-to-B Environment., , and . IMSA, page 152-157. IASTED/ACTA Press, (2002)A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency., and . VLSI Design, page 117-122. IEEE Computer Society, (2006)Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits., , and . ISLPED, page 245-249. ACM, (1998)