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Analysis of Open Loop Track-and-Hold Circuits., , and . ICECS, page 1236-1239. IEEE, (2007)Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs., , , and . ISCAS, page 1951-1954. IEEE, (2007)Parallel current-steering D/A Converters for Flexibility and Smartness., , , , and . ISCAS, page 1465-1468. IEEE, (2007)DDL-based calibration techniques for timing errors in current-steering DACs., , and . ISCAS, IEEE, (2006)Recognition of Real-Life Character Samples using a Structural Variation and Degradation Model., and . ICDAR, page 225-228. IEEE Computer Society, (1999)Predictive timing error calibration technique for RF current-steering DACs., , and . ISCAS, page 228-231. IEEE, (2008)Smart AD and DA converters., , , , , , and . ISCAS (4), page 4062-4065. IEEE, (2005)An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals., , , and . IEEE Trans. on Circuits and Systems, 59-I (5): 906-914 (2012)Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption., , , , and . Integration, 40 (3): 365-379 (2007)Sigma delta feedback DAC architectures for high accuracy and extremely low charge transfer., , and . ISCAS, page 1813-1816. IEEE, (2013)