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High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware.

, and . IEEE Trans. Computers, 57 (8): 1057-1071 (2008)

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Energy Performance of Floating-Point Matrix Multiplication on FPGAs., and . ERSA, page 316. CSREA Press, (2004)High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs., , and . IEEE Trans. Parallel Distrib. Syst., 18 (10): 1377-1392 (2007)Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems., and . IEEE Trans. Parallel Distrib. Syst., 18 (4): 433-448 (2007)Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores., , and . IPDPS, IEEE Computer Society, (2005)Document replication and distribution in extensible geographically distributed web servers., , and . J. Parallel Distrib. Comput., 63 (10): 927-944 (2003)Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores., , and . ERSA, page 119-128. CSREA Press, (2005)Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on FPGAs., and . IPDPS, IEEE Computer Society, (2004)High Performance Linear Algebra Operations on Reconfigurable Systems., and . SC, page 2. IEEE Computer Society, (2005)Load Balancing in Distributed Web Server Systems with Partial Document Replication., , and . ICPP, page 305-314. IEEE Computer Society, (2002)High-Performance and Parameterized Matrix Factorization on FPGAs., and . FPL, page 1-6. IEEE, (2006)