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Efficient Timing Analysis With Known False Paths Using Biclique Covering., , , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (5): 959-969 (2007)Improving the efficiency of static timing analysis with false paths., , , , , , , , , and . ICCAD, page 527-531. IEEE Computer Society, (2005)Fast adders in modern FPGAs., , , , , and . FPGA, page 250. ACM, (2004)An algebraic multigrid solver for analytical placement with layout based clustering., , , , , , , and . DAC, page 794-799. ACM, (2003)Total power-optimal pipelining and parallel processing under process variations in nanometer technology., , , , and . ICCAD, page 535-540. IEEE Computer Society, (2005)A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages., , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 511-519. Springer, (2003)A physical retiming algorithm for field programmable gate arrays., , , and . FPGA, page 247. ACM, (2003)Incremental physical resynthesis for timing optimization., , , and . FPGA, page 99-108. ACM, (2004)The effect of post-layout pin permutation on timing., , and . FPGA, page 41-50. ACM, (2005)Fast post-placement rewiring using easily detectable functional symmetries., , , and . DAC, page 286-289. ACM, (2000)