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Design methodology of configurable high performance packet parser for FPGA.

V. Pus, L. Kekely, and J. Korenek. DDECS, page 189-194. IEEE Computer Society, (2014)

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Nina Lukashina University of Stuttgart

Lukas Hauser University of Stuttgart

Lukas Münch University of Stuttgart

Lukas Reiner University of Stuttgart

Lukas Schmelzeisen University of Stuttgart

Other publications of authors with the same name

CRC based hashing in FPGA using DSP blocks.T. Závodník, L. Kekely, and V. Pus. DDECS, page 179-182. IEEE Computer Society, (2014)Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput.J. Cabal, P. Benácek, L. Kekely, M. Kekely, V. Pus, and J. Korenek. FPGA, page 249-258. ACM, (2018)Low-latency modular packet header parser for FPGA.V. Pus, L. Kekely, and J. Korenek. ANCS, page 77-78. ACM, (2012)Using DSP blocks to compute CRC hash in FPGA (abstract only).V. Pus, L. Kekely, and T. Závodník. FPGA, page 256. ACM, (2014)Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring.L. Kekely, V. Pus, P. Benácek, and J. Korenek. FPL, page 1-4. IEEE, (2014)Design methodology of configurable high performance packet parser for FPGA.V. Pus, L. Kekely, and J. Korenek. DDECS, page 189-194. IEEE Computer Society, (2014)General IDS Acceleration for High-Speed Networks.J. Kucera, L. Kekely, A. Piecek, and J. Korenek. ICCD, page 366-373. IEEE Computer Society, (2018)Memory Aware Packet Matching Architecture for High-Speed Networks.M. Kekely, L. Kekely, and J. Korenek. DSD, page 1-8. IEEE Computer Society, (2018)Accelerated Wire-Speed Packet Capture at 200 Gbps.L. Kekely, M. Spinler, S. Friedl, J. Sikora, and J. Korenek. FPL, page 455-456. IEEE Computer Society, (2018)Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput.L. Kekely, M. Spinler, S. Friedl, J. Sikora, J. Korenek, and V. Pus. FPT, page 381-384. IEEE, (2018)

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Disambiguation of "Kekely, Lukas"

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Design methodology of configurable high performance packet parser for FPGA.

Please choose a person to relate this publication to

Nina Lukashina University of Stuttgart

Lukas Hauser University of Stuttgart

Lukas Münch University of Stuttgart

Lukas Reiner University of Stuttgart

Lukas Schmelzeisen University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Kekely, Lukas"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design methodology of configurable high performance packet parser for FPGA.

Please choose a person to relate this publication to

Nina Lukashina University of Stuttgart

Lukas Hauser University of Stuttgart

Lukas Münch University of Stuttgart

Lukas Reiner University of Stuttgart

Lukas Schmelzeisen University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

Design methodology of configurable high performance packet parser for FPGA.