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Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks., , , , , and . IEEE Trans. Computers, 57 (11): 1482-1497 (2008)Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest., , , , , , , , , and 9 other author(s). J. Cryptographic Engineering, 4 (4): 259-274 (2014)A Reconfigurable Cell for a Multi-Style Asynchronous FPGA., , , , , and . ReCoSoC, page 15-22. Univ. Montpellier II, (2007)A fast pipelined multi-mode DES architecture operating in IP representation., , and . Integration, 40 (4): 479-489 (2007)Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints., , , , and . DATE, page 640-645. IEEE, (2009)Practical Setup Time Violation Attacks on AES., , and . EDCC, page 91-96. IEEE Computer Society, (2008)The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations., and . SEC, volume 181 of IFIP, page 589-600. Springer, (2005)FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems., , , and . ReConFig, page 47-55. IEEE Computer Society, (2006)Cryptographically Secure Shield for Security IPs Protection., , , , , , and . IEEE Trans. Computers, 66 (2): 354-360 (2017)Optimal side-channel attacks for multivariate leakages and multiple models., , , , and . J. Cryptographic Engineering, 7 (4): 331-341 (2017)