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Graphic rendering application profiling on a shared memory MPSOC architecture.

, , , and . DASIP, page 115-121. IEEE, (2011)

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Hierarchical Network-on-Chip for Embedded Many-Core Architectures., , , and . NOCS, page 189-196. IEEE Computer Society, (2010)SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications., , , , , and . VLSI-SoC, page 341-346. IEEE, (2010)Impact of power management on temperature and reliability evolution for an embedded many-core architecture., , , and . ARCS Workshops, VDE-Verlag, (2011)A small footprint interleaved multithreaded processor for embedded systems., , , , , , and . ICECS, page 685-690. IEEE, (2011)Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems., , , and . DSD, page 575-581. IEEE Computer Society, (2009)A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints., , , and . IPDPS, IEEE Computer Society, (2002)DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency., , and . EURASIP J. Emb. Sys., (2008)Architectures reconfigurable et faible consommation. Réalité ou prospective ?, and . Technique et Science Informatiques, 26 (5): 595-621 (2007)SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications., and . IFMT, page 6:1-6:12. ACM, (2010)