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An overall gain estimation algorithm for all digital phase locked loops., , , , , and . ISCAS, page 325-328. IEEE, (2014)Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter., , and . IEEE Trans. on Circuits and Systems, 57-II (12): 941-945 (2010)A Novel Hybrid Polar-I/Q Modulation Method relaxing RF Phase Modulator Design Requirements., , , , , , and . PRIME, page 181-184. IEEE, (2018)Reconstruction of Two-Periodic Nonuniformly Sampled Band-Limited Signals Using a Discrete-Time Differentiator and a Time-Varying Multiplier., and . IEEE Trans. on Circuits and Systems, 54-II (7): 616-620 (2007)A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 65-I (12): 4390-4403 (2018)Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator-Multiplier Cascade., and . IEEE Trans. on Circuits and Systems, 55-I (8): 2273-2286 (2008)A DCO Gain Estimation Algorithm for Digital Phase Locked Loops., , , , , and . EW, VDE-Verlag, (2013)Combined Effect of Loop Delay and Reference Clock Jitter in First-order Digital Bang-bang Phase-locked Loops., and . ISCAS, page 2393-2396. IEEE, (2009)Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory., , and . IEEE Trans. on Circuits and Systems, 57-I (9): 2367-2380 (2010)Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter., and . IEEE Trans. on Circuits and Systems, 58-II (6): 331-335 (2011)