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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean, and P. Wambacq. ESSDERC, page 102-105. IEEE, (2014)

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Ivan Solonenko University of Stuttgart

Ivan Buntic University of Stuttgart

Sergio Ivan Caceres Castro University of Stuttgart

Other publications of authors with the same name

A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network.H. Zahedmanesh, I. Ciofi, O. Zografos, M. Badaroglu, and K. Croes. SLIP, page 1-7. IEEE, (2021)Impact of process variability on BEOL TDDB lifetime model assessment.K. Croes, D. Kocaay, I. Ciofi, J. Bömmels, and Z. Tokei. IRPS, page 5. IEEE, (2015)Intrinsic reliability of local interconnects for N7 and beyond.K. Croes, A. Lesniewska, C. Wu, I. Ciofi, A. Banczerowska, B. Briggs, S. Demuynck, Z. Tokei, J. Bömmels, Y. Saad and 1 other author(s). IRPS, page 2. IEEE, (2015)Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.H. Zahedmanesh, M. Gonzalez, I. Ciofi, K. Croes, J. Bömmels, and Z. Tokei. Microelectronics Reliability, (2016)Temperature controlled oven for low noise measurement systems for electromigration characterization.C. Ciofi, I. Ciofi, S. Pascoli, and B. Neri. IEEE Trans. Instrumentation and Measurement, 49 (3): 546-549 (2000)Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques.C. Kerner, I. Ciofi, T. Chiarella, and S. Huylenbroeck. ESSDERC, page 221-225. IEEE, (2012)Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing.D. Kocaay, P. Roussel, K. Croes, I. Ciofi, A. Lesniewska, and I. Wolf. IRPS, page 10-1. IEEE, (2018)Insights into metal drift induced failure in MOL and BEOL.C. Wu, O. Pedreira, A. Lesniewska, Y. Li, I. Ciofi, Z. Tokei, and K. Croes. IRPS, page 3. IEEE, (2018)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.T. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)

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Disambiguation of "Ciofi, Ivan"

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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Ivan Solonenko University of Stuttgart

Ivan Buntic University of Stuttgart

Sergio Ivan Caceres Castro University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Ciofi, Ivan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Please choose a person to relate this publication to

Ivan Solonenko University of Stuttgart

Ivan Buntic University of Stuttgart

Sergio Ivan Caceres Castro University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.