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High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree., , and . IEEE Trans. Computers, 34 (9): 789-796 (1985)Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem., and . IEEE Trans. Computers, 41 (7): 887-891 (1992)On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic., and . IEEE Trans. Computers, 36 (11): 1310-1317 (1987)A Linear Storage Space Algorithm for a Reference Structure Index., , , and . Inf. Process. Lett., 7 (2): 66-71 (1978)Organization of quasi-consecutive retrieval files., , and . Inf. Syst., 4 (3): 23-33 (1979)A Longest Common Subsequence Algorithm Suitable for Similar Text Strings., , and . Acta Inf., (1982)An on-line error-detectable high-speed array divider., and . Systems and Computers in Japan, 22 (1): 21-27 (1991)Infinity-Regular Temporal Logic and its Model Checking Problem., , and . Theor. Comput. Sci., 103 (2): 191-204 (1992)Fault simulation for multiple faults by Boolean function manipulation., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (4): 531-535 (1994)Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets., , and . ICCAD, page 550-553. IEEE Computer Society, (1991)