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Column readout circuit with dual integration CDS for infrared imagers.

, , , and . IEICE Electronic Express, 13 (7): 20151037 (2016)

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Charge-Recovery Computing on Silicon., , and . IEEE Trans. Computers, 54 (6): 651-659 (2005)True single-phase adiabatic circuitry., and . IEEE Trans. VLSI Syst., 9 (1): 52-63 (2001)A true single-phase energy-recovery multiplier., , and . IEEE Trans. VLSI Syst., 11 (2): 194-207 (2003)1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS., , , , and . IEEE Trans. VLSI Syst., 22 (3): 585-592 (2014)Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files., , and . IEEE Trans. on Circuits and Systems, 60-I (4): 965-974 (2013)Fine-grain real-time reconfigurable pipelining., , and . IBM Journal of Research and Development, 47 (5-6): 599-610 (2003)A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface., , , , , , , , , and . ISSCC, page 494-496. IEEE, (2011)Introduction to the Special Issue on the 2006 Asian Solid-State Circuits Conference (A-SSCC'06)., and . J. Solid-State Circuits, 42 (11): 2323-2325 (2007)Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier., , and . ARVLSI, page 42-58. IEEE Computer Society, (2001)A resonant clock generator for single-phase adiabatic systems., , and . ISLPED, page 159-164. ACM, (2001)