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Disambiguation of "Hou, Chih-Sheng"

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Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.

, , , , , , , and . ATS, page 143-148. IEEE Computer Society, (2014)

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Dr. Shaoxiang Sheng University of Stuttgart

Sheng Ding University of Stuttgart

Chih-Hao Wang University of Stuttgart

 

Other publications of authors with the same name

Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost., , and . VTS, page 21-26. IEEE Computer Society, (2010)An FPGA-based test platform for analyzing data retention time distribution of DRAMs., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Testing Disturbance Faults in Various NAND Flash Memories., and . Asian Test Symposium, page 221-226. IEEE Computer Society, (2013)Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs., and . VTS, page 1-6. IEEE Computer Society, (2013)Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs., , , , , , , and . ATS, page 143-148. IEEE Computer Society, (2014)Memory Built-in Self-Repair Planning Framework for RAMs in SoCs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (11): 1731-1743 (2011)A Built-in Method to Repair SoC RAMs in Parallel., , and . IEEE Design & Test of Computers, 27 (6): 46-57 (2010)Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs., , and . DELTA, page 3-7. IEEE Computer Society, (2010)Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults., , and . IEEE Trans. VLSI Syst., 18 (9): 1361-1366 (2010)Testing Disturbance Faults in Various NAND Flash Memories., and . J. Electronic Testing, 30 (6): 643-652 (2014)