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Fault-Tolerant Array Processors Using Single-Track Switches.

, , and . IEEE Trans. Computers, 38 (4): 501-514 (1989)

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Real-Time Configuration for Fault-Tolerant VLSI Array Processors., , and . RTSS, page 46-54. IEEE Computer Society, (1986)In-place delay constrained power optimization using functional symmetries., , and . DATE, page 377-382. IEEE Computer Society, (2001)Fault-Tolerant Array Processors Using Single-Track Switches., , and . IEEE Trans. Computers, 38 (4): 501-514 (1989)Single-Pass Redundancy Addition and Removal., and . ICCAD, page 606-609. IEEE Computer Society, (2001)Fast postplacement optimization using functional symmetries., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (1): 102-118 (2004)A new reasoning scheme for efficient redundancy addition and removal., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (7): 945-951 (2003)Graceful Degradation Schemes for Static/Dynamic Wavefront Arrays., , and . ICPP (1), page 249-255. Pennsylvania State University Press, (1988)Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques., , and . DAC, page 97-102. ACM, (2001)Who are the alternative wires in your neighborhood? (alternative wires identification without search)., and . ACM Great Lakes Symposium on VLSI, page 103-108. ACM, (2001)ATPG-based logic synthesis: an overview., and . ICCAD, page 786-789. ACM / IEEE Computer Society, (2002)