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The impact of clock gating schemes on the power dissipation of synthesizable register files., , , , and . ISCAS (2), page 609-612. IEEE, (2004)Built-in self test architectures for multistage interconnection networks., , and . ED&TC, page 176-180. IEEE Computer Society, (1996)Low Power CORDIC Implementation Using Redundant Number Representation., , and . ASAP, page 154-161. IEEE Computer Society, (1997)An image filter technique to relax particle image velocimetry., , , , and . EUSIPCO, page 283-287. IEEE, (2011)Low power synthesizable register files for processor and IP cores., , , , and . Integration, 39 (2): 131-155 (2006)Memory-efficient parallelization of JPEG-LS with relaxed context update., , , , , and . PCS, page 142-145. IEEE, (2010)Architecture for parallel marker-free variable length streams decoding., , , , , , and . J. Real-Time Image Processing, 16 (6): 2127-2146 (2019)Information about WZ18-20, , , , , , , and . Dataset, (2021)Information about WZ10-09, , , , , , , and . Dataset, (2021)Information about WZ17-20, , , , , , , and . Dataset, (2021)