Author of the publication

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture.

, , , , and . Int. J. Reconfig. Comp., (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Amagasaki, Motoki
add a person with the name Amagasaki, Motoki
 

Other publications of authors with the same name

Evaluation of fault tolerant technique based on homogeneous FPGA architecture., , , , , and . VLSI-SoC, page 225-230. IEEE, (2012)A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)., , , , , and . FPGA, page 271. ACM, (2013)An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture., , , , and . Int. J. Reconfig. Comp., (2008)A novel states recovery technique for the TMR softcore processor., , , , , and . FPL, page 543-546. IEEE, (2009)An Easily Testable Routing Architecture and Efficient Test Technique., , , , and . FPL, page 291-294. IEEE Computer Society, (2011)A 3D FPGA Architecture to Realize Simple Die Stacking., , , , and . IPSJ Trans. System LSI Design Methodology, (2015)FPGA Design Framework Combined with Commercial VLSI CAD., , , , , and . IEICE Transactions, 96-D (8): 1602-1612 (2013)Three-dimensional stacking FPGA architecture using face-to-face integration., , , , , and . VLSI-SoC, page 192-197. IEEE, (2013)Architecture exploration of 3D FPGA to minimize internal layer connection., , , , , and . VLSI-SoC, page 110-115. IEEE, (2015)Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration., , , , , and . FCCM, page 47-54. IEEE Computer Society, (2010)