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High Level Fault Injection for Attack Simulation in Smart Cards.

, , , , , and . Asian Test Symposium, page 118-121. IEEE Computer Society, (2004)

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Horizontal and vertical HW/SW co-design flows for power aware smart card designs., , , , and . IJES, 3 (1/2): 93-106 (2007)A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines., , , and . DSD, page 212-219. IEEE Computer Society, (2001)Fault insertion testing of a novel CPLD-based fail-safe system., , , and . DATE, page 214-219. IEEE, (2009)Case study on multiple fault dependability and security evaluations., , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (2): 218-227 (2013)Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards., , , , , and . DATE, page 300-305. IEEE Computer Society, (2004)Automatic Testbench Generation for Simulation-based Verification of Safety-critical Systems in UML., , , , , and . PECCS, page 70-75. SciTePress, (2016)Power consumption profile analysis for security attack simulation in smart cards at high abstraction level., , , , , and . EMSOFT, page 214-217. ACM, (2005)Using field strength scaling to save energy in mobile HF-band RFID-systems., , , , , and . EURASIP J. Emb. Sys., (2013)Automotive Embedded Systems - The Migration Challenges to a Time Triggered Paradigm., , , , , and . Solutions on Embedded Systems, volume 81 of Lecture Notes in Electrical Engineering, Springer, (2011)System side-channel leakage emulation for HW/SW security coverification of MPSoCs., , , , , and . DDECS, page 139-144. IEEE, (2012)