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Disambiguation of "Cawley, Seamus"

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The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans.

, , , , , , , , , , , , , , , , and . Living Machines, volume 8608 of Lecture Notes in Computer Science, page 436-438. Springer, (2014)

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Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures., , , , , , and . IJCCI (NCTA), page 128-137. SciTePress, (2011)The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans., , , , , , , , , and 7 other author(s). Living Machines, volume 8608 of Lecture Notes in Computer Science, page 436-438. Springer, (2014)Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations., , , , , , and . IEEE Trans. Parallel Distrib. Syst., 24 (12): 2451-2461 (2013)Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network., , , , , , , , and . Neural Processing Letters, 38 (2): 131-153 (2013)Remote FPGA Lab with Interactive Control and Visualisation Interface., , , , , , , , and . FPL, page 496-499. IEEE Computer Society, (2011)Hardware spiking neural network prototyping and application., , , , , , and . Genetic Programming and Evolvable Machines, 12 (3): 257-280 (2011)Enhancing learning of digital systems using a remote FPGA lab., and . ReCoSoC, page 1-8. IEEE, (2011)Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers., , , , , , and . Neural Networks, (2012)Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC., , , , , , , , , and . RSP, page 76-82. IEEE, (2018)Fixed latency on-chip interconnect for hardware spiking neural network architectures., , , , , , , , and . Parallel Computing, 39 (9): 357-371 (2013)