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Dynamic Verification of Sequential Consistency.

, and . ISCA, page 482-493. IEEE Computer Society, (2005)

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Error Detection Using Dynamic Dataflow Verification., and . PACT, page 104-118. IEEE Computer Society, (2007)Robustness and security of a wavelet-based CBIR hashing algorithm., and . MM&Sec, page 140-145. ACM, (2006)Lazy Error Detection for Microprocessor Functional Units., , , and . DFT, page 361-369. IEEE Computer Society, (2007)Dynamic Verification of Sequential Consistency., and . ISCA, page 482-493. IEEE Computer Society, (2005)Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures., and . IEEE Trans. Dependable Sec. Comput., 6 (1): 18-31 (2009)Argus: Low-Cost, Comprehensive Error Detection in Simple Cores., , and . MICRO, page 210-222. IEEE Computer Society, (2007)Architectures for online error detection and recovery in multicore processors., , , , , , , , and . DATE, page 533-538. IEEE, (2011)Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures., and . HPCA, page 145-156. IEEE Computer Society, (2007)Analysis of a wavelet-based robust hash algorithm., and . Security, Steganography, and Watermarking of Multimedia Contents, volume 5306 of Proceedings of SPIE, page 772-783. SPIE, (2004)An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2., , and . SIGMETRICS, page 121-122. ACM, (2011)