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Disambiguation of "Camus, Vincent"

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Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems.

, , and . ISVLSI, page 476-480. IEEE Computer Society, (2015)

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Vincent Bezold University of Stuttgart

Vincent Reß University of Stuttgart

Vincent Wagner University of Stuttgart

Vincent Carpenter University of Stuttgart

Vincent Gramm University of Stuttgart

 

Other publications of authors with the same name

Energy-efficient inexact speculative adder with high performance and accuracy control., , and . ISCAS, page 45-48. IEEE, (2015)Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders., , , , and . NGCAS, page 41-44. IEEE, (2017)Approximate 32-bit floating-point unit design with 53% power-area product reduction., , , , and . ESSCIRC, page 465-468. IEEE, (2016)Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems., , and . ISVLSI, page 476-480. IEEE Computer Society, (2015)A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision., , and . DAC, page 127:1-127:6. ACM, (2016)Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (4): 746-757 (2018)Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (4): 697-711 (2019)Automatic generation of inexact digital circuits by gate-level pruning., , , and . ISCAS, page 173-176. IEEE, (2015)Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing., , and . AICAS, page 57-61. IEEE, (2019)Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis., , , , and . SoCC, page 158-162. IEEE, (2018)