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Disambiguation of "Zerbe, Jared"

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Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.

, , , , , , , , , , , , and . CICC, page 709-716. IEEE, (2005)

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Jared Miller University of Stuttgart

 

Other publications of authors with the same name

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR., , , , , , , , , and 9 other author(s). ISSCC, page 228-599. IEEE, (2007)Power-efficient I/O design considerations for high-bandwidth applications., , , , , , , , and . CICC, page 1-8. IEEE, (2011)A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 49 (4): 1048-1062 (2014)A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on., , , , , and . CICC, page 1-4. IEEE, (2012)Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric., , , , , , , , , and . J. Solid-State Circuits, 43 (9): 2144-2156 (2008)Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system., , , , , , , , , and 3 other author(s). CICC, page 709-716. IEEE, (2005)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 50 (4): 814-827 (2015)Transition-limiting codes for 4-PAM signaling in high speed serial links., , , and . GLOBECOM, page 3747-3751. IEEE, (2003)