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A compression-based area-efficient recovery architecture for nonvolatile processors.

Y. Wang, Y. Liu, Y. Liu, D. Zhang, S. Li, B. Sai, M. Chiang, and H. Yang. DATE, page 1519-1524. IEEE, (2012)

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Dr. Barbara Meisterernst University of Stuttgart

Florian Meinert University of Stuttgart

Univ. -Prof. Dr. -Ing. Karsten Meier University of Stuttgart

Robert Meissner

Johanna Meier University of Stuttgart

Other publications of authors with the same name

Novel full-chip gridless routing considering double-via insertion.H. Chen, M. Chiang, Y. Chang, L. Chen, and B. Han. DAC, page 755-760. ACM, (2006)Register placement for high-performance circuits.M. Chiang, T. Okamoto, and T. Yoshimura. DATE, page 1470-1475. IEEE, (2009)A compression-based area-efficient recovery architecture for nonvolatile processors.Y. Wang, Y. Liu, Y. Liu, D. Zhang, S. Li, B. Sai, M. Chiang, and H. Yang. DATE, page 1519-1524. IEEE, (2012)Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density.S. Chen, J. Shen, W. Guo, M. Chiang, and T. Yoshimura. IEICE Transactions, 93-A (12): 2372-2379 (2010)Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs.S. Chen, L. Ge, M. Chiang, and T. Yoshimura. IEICE Transactions, 92-A (4): 1080-1087 (2009)A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M. Chiang, Y. Yan, B. Sai, and H. Yang. ESSCIRC, page 149-152. IEEE, (2012)Full-Chip Routing Considering Double-Via Insertion.H. Chen, M. Chiang, Y. Chang, L. Chen, and B. Han. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (5): 844-857 (2008)Lagrangian relaxation based register placement for high-performance circuits.M. Chiang, T. Okamoto, and T. Yoshimura. ISQED, page 511-516. IEEE Computer Society, (2009)PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.Y. Wang, Y. Liu, S. Li, X. Sheng, D. Zhang, M. Chiang, B. Sai, X. Hu, and H. Yang. IEEE Trans. VLSI Syst., 22 (7): 1491-1505 (2014)

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Disambiguation of "Chiang, Mei-Fang"

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A compression-based area-efficient recovery architecture for nonvolatile processors.

Please choose a person to relate this publication to

Dr. Barbara Meisterernst University of Stuttgart

Florian Meinert University of Stuttgart

Univ. -Prof. Dr. -Ing. Karsten Meier University of Stuttgart

Robert Meissner

Johanna Meier University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chiang, Mei-Fang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A compression-based area-efficient recovery architecture for nonvolatile processors.

Please choose a person to relate this publication to

Dr. Barbara Meisterernst University of Stuttgart

Florian Meinert University of Stuttgart

Univ. -Prof. Dr. -Ing. Karsten Meier University of Stuttgart

Robert Meissner

Johanna Meier University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A compression-based area-efficient recovery architecture for nonvolatile processors.