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Disambiguation of "Lam, Chung Hon"

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A novel CMOS compatible embedded nonvolatile memory with zero process adder.

, , , , and . MTDT, page 9-12. IEEE Computer Society, (2005)

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Dr. Grazia Lamanna University of Stuttgart

Clemens Honold

Phi-Long Chung University of Stuttgart

Lena Lambers

Maike Lambarth University of Stuttgart

 

Other publications of authors with the same name

A novel CMOS compatible embedded nonvolatile memory with zero process adder., , , , and . MTDT, page 9-12. IEEE Computer Society, (2005)Nanoscale electronic synapses using phase change devices., , , , , , , , , and 5 other author(s). JETC, 9 (2): 12:1-12:20 (2013)Ultralow-power SRAM technology., , , , , , , , , and 12 other author(s). IBM Journal of Research and Development, 47 (5-6): 553-566 (2003)Transition-metal-oxide-based resistance-change memories., , , , , , , , , and 5 other author(s). IBM Journal of Research and Development, 52 (4-5): 481-492 (2008)Phase-change random access memory: A scalable technology., , , , , , , , , and 1 other author(s). IBM Journal of Research and Development, 52 (4-5): 465-480 (2008)Recent Progress in Phase-Change Memory Technology., , , , , , , , , and 2 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 146-162 (2016)Multilevel phase-change memory., , , , , , and . ICECS, page 1017-1020. IEEE, (2010)A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 60-I (6): 1521-1533 (2013)A half-micron CMOS logic generation., , , , , , , , , and 14 other author(s). IBM Journal of Research and Development, 39 (1-2): 215-228 (1995)Programming algorithms for multilevel phase-change memory., , , , , , and . ISCAS, page 329-332. IEEE, (2011)