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Disambiguation of "Homma, Naofumi"

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Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations.

, , and . IEICE Transactions, 97-D (9): 2270-2277 (2014)

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Other publications of authors with the same name

Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic., , and . IEEE Trans. Computers, 63 (10): 2604-2613 (2014)Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language., , , , and . Multiple-Valued Logic and Soft Computing, 15 (4): 329-340 (2009)A Formal Approach to Designing Multiple-Valued Arithmetic Circuits., , and . Multiple-Valued Logic and Soft Computing, 24 (1-4): 21-34 (2015)Graph-based evolutionary design of arithmetic circuits., , , , and . IEEE Trans. Evolutionary Computation, 6 (1): 86-100 (2002)An on-chip glitchy-clock generator for testing fault injection attacks., , , , and . J. Cryptographic Engineering, 1 (4): 265-270 (2011)A Formal Approach to Designing Cryptographic Processors Based on $GF(2^m)$ Arithmetic Circuits., , and . IEEE Trans. Information Forensics and Security, 7 (1): 3-13 (2012)Chosen-message SPA attacks against FPGA-based RSA hardware implementations., , , and . FPL, page 35-40. IEEE, (2008)Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques., , , , , and . DATE, page 1004-1009. IEEE, (2011)Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage., , , , , , , , , and 4 other author(s). IEICE Transactions, 97-C (4): 272-279 (2014)Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams., , , and . ISMVL, page 31. IEEE Computer Society, (2007)