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Disambiguation of "Vasudevan, Dilip P."

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Ultra Low Power Asynchronous Charge Sharing Logic.

, , , and . J. Low Power Electronics, 8 (4): 526-534 (2012)

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P. Hommel

P. Abegglen

P. Krasteva

P. E. Bl\"ochl

Philipp P. Hallmen

 

Other publications of authors with the same name

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits., , and . DFT, page 371-379. IEEE Computer Society, (2005)A Technique for Modular Design of Self-Checking Carry-Select Adder., and . DFT, page 325-333. IEEE Computer Society, (2005)Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays., and . DELTA, page 149-156. IEEE Computer Society, (2006)3D photonics as enabling technology for deep 3D DRAM stacking., , , , , , and . MEMSYS, page 206-221. ACM, (2019)Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies., , , , and . ISC Workshops, volume 10524 of Lecture Notes in Computer Science, page 115-123. Springer, (2017)PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments., , , and . ISPASS, page 139-140. IEEE, (2019)Online Testable Reversible Logic Circuit Design using NAND Blocks., , and . DFT, page 324-331. IEEE Computer Society, (2004)A Novel Approach for On-line Testable Reversible Logic Circuit Desig., , and . Asian Test Symposium, page 325-330. IEEE Computer Society, (2004)Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing., , and . 3DIC, page 1-8. IEEE, (2011)Reversible-logic design with online testability., , , and . IEEE Trans. Instrumentation and Measurement, 55 (2): 406-414 (2006)