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Disambiguation of "Singh, Adit D."

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A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.

. DFT, page 422-422. IEEE Computer Society, (2009)

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D. Marino

Arijit Singha Hazari University of Stuttgart

Prakhar Singhal University of Stuttgart

D. Roth

D. Inkermann

 

Other publications of authors with the same name

On the Effect of Defect Clustering on Test Transparency and IC Test Optimization., and . IEEE Trans. Computers, 45 (6): 753-757 (1996)A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)., and . IEEE Trans. VLSI Syst., 14 (11): 1216-1226 (2006)Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations., , , , and . VLSI Design, page 711-716. IEEE Computer Society, (2007)A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI., and . ICPP (1), page 261-265. Pennsylvania State University Press, (1989)Distinguishing Resistive Small Delay Defects from Random Parameter Variations., and . Asian Test Symposium, page 325-330. IEEE Computer Society, (2010)Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing., , , and . Asian Test Symposium, page 237-240. IEEE Computer Society, (2009)Relating Yield Models to Burn-In Fall-Out in Time., and . ITC, page 77-84. IEEE Computer Society, (2003)Modelling correlated transient failures in fault-tolerant systems., and . FTCS, page 374-381. IEEE Computer Society, (1989)Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits., , and . European Test Symposium, page 24-29. IEEE Computer Society, (2004)Extending integrated-circuit yield-models to estimate early-life reliability., , and . IEEE Trans. Reliability, 52 (3): 296-300 (2003)