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Design optimization for capacitive-resistively driven on-chip global interconnect.

J. Jiang, W. He, J. Wei, Q. Wang, and Z. Mao. IEICE Electronic Express, 12 (8): 20150111 (2015)

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Chenming Jiang University of Stuttgart

Xiao Fei University of Stuttgart

Mathias Feinler University of Stuttgart

Carolin Feifel University of Stuttgart

Dr. -Ing. Marius Feilhauer University of Stuttgart

Other publications of authors with the same name

A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.X. Wang, J. Jiang, Z. Mao, B. Ge, and X. Zhao. ICECS, page 528-531. IEEE, (2011)Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.W. Sheng, W. He, J. Jiang, and Z. Mao. IPDPS Workshops, page 425-430. IEEE Computer Society, (2012)Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.J. Jiang, Z. Mao, W. Sheng, Q. Wang, and W. He. Journal of Circuits, Systems, and Computers, 25 (10): 1-31 (2016)Design optimization for capacitive-resistively driven on-chip global interconnect.J. Jiang, W. He, J. Wei, Q. Wang, and Z. Mao. IEICE Electronic Express, 12 (8): 20150111 (2015)A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.C. Wang, Q. Wang, and J. Jiang. ASICON, page 629-632. IEEE, (2011)A New Cellular-Based Redundant TSV Structure for Clustered Faults.Q. Wang, Z. Liu, J. Jiang, N. Jing, and W. Sheng. IEEE Trans. VLSI Syst., 27 (2): 458-467 (2019)A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.S. Zheng, H. You, G. He, Q. Wang, T. Si, J. Jiang, J. Jin, and N. Jing. ISCAS, page 1-5. IEEE, (2019)Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.Z. Chen, Q. Wang, J. Xie, J. Tian, J. Jiang, Y. Li, and W. Yin. ISCAS, page 2646-2649. IEEE, (2013)A clock-less transceiver for global interconnect.J. Jiang, X. Wang, W. Sheng, W. He, and Z. Mao. VLSI-SoC, page 184-187. IEEE, (2011)Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.N. Jing, J. Zhou, J. Jiang, X. Chen, W. He, and Z. Mao. ICCAD, page 764-769. IEEE, (2015)

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Disambiguation of "Jiang, Jian-Fei"

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Design optimization for capacitive-resistively driven on-chip global interconnect.

Please choose a person to relate this publication to

Chenming Jiang University of Stuttgart

Xiao Fei University of Stuttgart

Mathias Feinler University of Stuttgart

Carolin Feifel University of Stuttgart

Dr. -Ing. Marius Feilhauer University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Jiang, Jian-Fei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design optimization for capacitive-resistively driven on-chip global interconnect.

Please choose a person to relate this publication to

Chenming Jiang University of Stuttgart

Xiao Fei University of Stuttgart

Mathias Feinler University of Stuttgart

Carolin Feifel University of Stuttgart

Dr. -Ing. Marius Feilhauer University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Design optimization for capacitive-resistively driven on-chip global interconnect.