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Distributed Data Cache Designs for Clustered VLIW Processors.

, , and . IEEE Trans. Computers, 54 (10): 1227-1241 (2005)

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A detailed methodology to compute Soft Error Rates in advanced technologies., , , and . DATE, page 217-222. IEEE, (2016)Online error detection and correction of erratic bits in register files., , , , and . IOLTS, page 81-86. IEEE Computer Society, (2009)On-Line Failure Detection and Confinement in Caches., , , , and . IOLTS, page 3-9. IEEE Computer Society, (2008)Efficient resources assignment schemes for clustered multithreaded processors., , and . IPDPS, page 1-12. IEEE, (2008)A Quantitative Assessment of Thread-Level Speculation Techniques., and . IPDPS, page 595-601. IEEE Computer Society, (2000)A Power-Efficient Co-designed Out-of-Order Processor., , and . SBAC-PAD, page 1-8. IEEE Computer Society, (2011)Beforehand Migration on D-NUCA Caches., , , and . PACT, page 197-198. IEEE Computer Society, (2011)Swing module scheduling: a lifetime-sensitive approach., , , and . IEEE PACT, page 80-86. IEEE Computer Society, (1996)Optimizing cache miss equations polyhedra., , , and . SIGARCH Computer Architecture News, 28 (1): 43-52 (2000)CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference., , and . IEEE Micro, 39 (5): 36-45 (2019)