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High-Level Specification of Runtime Reconfigurable Designs., and . ERSA, page 280-283. CSREA Press, (2007)A Sandbox for Exploring the OpenFire Processor., , and . ERSA, page 248-251. CSREA Press, (2007)Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug., , and . FPL, page 518-523. IEEE Computer Society, (2011)A Methodology for Generating Application-Specific Heterogeneous Processor Arrays., , and . HICSS, IEEE Computer Society, (2006)PATIS: Using partial configuration to improve static FPGA design productivity., , , , , and . IPDPS Workshops, page 1-8. IEEE, (2010)High-Level Abstractions and Modular Debugging for FPGA Design Validation., , and . TRETS, 7 (1): 2:1-2:22 (2014)Using partial reconfiguration and high-level models to accelerate FPGA design validation., , , , , , and . FPT, page 341-344. IEEE, (2010)Accelerating FPGA development through the automatic parallel application of standard implementation tools., , , , , , and . FPT, page 53-60. IEEE, (2010)Examining the Viability of FPGA Supercomputing., and . EURASIP J. Emb. Sys., (2007)Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms., , , , and . HICSS, IEEE Computer Society, (2006)