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A 0.8V 6.4µW compact mixed-signal front-end for neural implants.

, , and . ISCAS, page 2223-2226. IEEE, (2012)

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Serial-Link Bus: A Low-Power On-Chip Bus Architecture., , , , and . IEEE Trans. on Circuits and Systems, 56-I (9): 2020-2032 (2009)Low-power on-chip bus architecture using dynamic relative delays., and . SoCC, page 233-236. IEEE, (2004)A novel digital loop filter architecture for bang-bang ADPLL., , , , , , , and . SoCC, page 45-50. IEEE, (2012)Effect of relative delay on the dissipated energy in coupled interconnects., and . ISCAS (2), page 525-528. IEEE, (2004)A novel power gated digitally controlled oscillator., , and . ICEAC, page 1-4. IEEE, (2011)High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network., , and . IntelliSys (1), volume 868 of Advances in Intelligent Systems and Computing, page 655-663. Springer, (2018)Formal derivation of optimal active shielding for low-power on-chip buses., and . ICCAD, page 800-807. IEEE Computer Society / ACM, (2004)A 16Gbps low power self-timed SerDes transceiver for multi-core communication., , , and . ISCAS, page 1660-1663. IEEE, (2012)Optimum positioning of interleaved repeaters in bidirectional buses., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (3): 461-469 (2005)The importance of including thermal effects in estimating the effectiveness of power reduction techniques., , and . CICC, page 301-304. IEEE, (2005)