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Disambiguation of "Chen, Yuan-Ho"

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Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG.

, , , , and . IEEE Trans. VLSI Syst., 20 (2): 385-389 (2012)

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Jingshan Chen University of Stuttgart

Optimization-based trajectory planning for transport collaboration of heterogeneous systems, , , and . Automatisierungstechnik, 72 (2): 80-90 (2024)

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Lidar-based virtual load sensors for mooring lines using artificial neural networks, , and . EERA Deepwind Conference 2023, 2626, page 012036. Institute of Physics, (2023)

Yiwen Yuan University of Stuttgart

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

 

Other publications of authors with the same name

A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique., , , , and . Journal of Circuits, Systems, and Computers, (2014)A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications., , , and . IEEE Trans. on Circuits and Systems, 58-II (4): 215-219 (2011)Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit.. IEEE Trans. on Circuits and Systems, 62-II (9): 851-855 (2015)Integrated model of hot spring service quality perceptions under uncertainty., , and . Appl. Soft Comput., 12 (8): 2352-2361 (2012)Implementation of FPGA-based Accelerator for Deep Neural Networks., , and . DDECS, page 1-4. IEEE, (2019)E-leadership effectiveness in virtual teams: motivating language perspective., , , and . Industrial Management and Data Systems, 114 (3): 421-437 (2014)High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree., , and . IEEE Trans. VLSI Syst., 19 (4): 709-714 (2011)A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers., and . IEEE Trans. on Circuits and Systems, 59-I (3): 594-603 (2012)Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation., , and . Sensors, 17 (10): 2288 (2017)Cost-effective multi-standard video transform core using time-sharing architecture., and . EURASIP J. Adv. Sig. Proc., (2019)