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The Power-Performance Tradeoffs of the Intel Xeon Phi on HPC Applications.

, , , , , , and . IPDPS Workshops, page 1448-1456. IEEE Computer Society, (2014)

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A Simplified and Accurate Model of Power-Performance Efficiency on Emergent GPU Architectures., , , and . IPDPS, page 673-686. IEEE Computer Society, (2013)Modeling and evaluating energy-performance efficiency of parallel processing on multicore based power aware systems., , and . IPDPS, page 1-8. IEEE, (2009)Critical path-based thread placement for NUMA systems., , , , , and . SIGMETRICS Performance Evaluation Review, 40 (2): 106-112 (2012)A Statistical-Empirical Hybrid Approach to Hierarchical Memory Analysis., and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 141-148. Springer, (2000)SeeMore., and . SIGGRAPH Art Gallery, page 414-415. ACM, (2014)HpMC: An Energy-aware Management System of Multi-level Memory Architectures., , , , , , and . MEMSYS, page 167-178. ACM, (2015)Power saving experiments for large-scale global optimisation., , , , , and . IJPEDS, 25 (5): 381-400 (2010)An ISO-Energy-Efficient Approach to Scalable System Power-Performance Optimization., , and . CLUSTER, page 262-271. IEEE Computer Society, (2011)Performance-constrained Distributed DVS Scheduling for Scientific Applications on Power-aware Clusters., , and . SC, page 34. IEEE Computer Society, (2005)Predicting and Evaluating Distributed Communication Performance., and . SC, page 43. IEEE Computer Society, (2004)