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Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.

, , , and . HiPEAC, volume 4917 of Lecture Notes in Computer Science, page 147-160. Springer, (2008)

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Prototyping and Programming Tightly Coupled Accelerators., , , and . PARCO, volume 19 of Advances in Parallel Computing, page 720-727. IOS Press, (2009)Implementation and Optimization of the OpenMP Accelerator Model for the TI Keystone II Architecture., , , and . IWOMP, volume 8766 of Lecture Notes in Computer Science, page 202-214. Springer, (2014)Introduction., , , , , and . Euro-Par, volume 5704 of Lecture Notes in Computer Science, page 837-838. Springer, (2009)Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture., , and . OM@PLDI, page 138-144. ACM, (2001)Implementing OpenMP on a high performance embedded multicore MPSoC., , , , , and . IPDPS, page 1-8. IEEE, (2009)Affinity-based cluster assignment for unrolled loops., , and . ICS, page 107-116. ACM, (2002)OpenMP on the Low-Power TI Keystone II ARM/DSP System-on-Chip., , , , , , and . IWOMP, volume 8122 of Lecture Notes in Computer Science, page 114-127. Springer, (2013)Exploiting DMA for Performance and Energy Optimized STREAM on a DSP., , , , , and . IPDPS Workshops, page 805-814. IEEE Computer Society, (2014)Unleashing the high-performance and low-power of multi-core DSPs for general-purpose HPC., , , , , and . SC, page 26. IEEE/ACM, (2012)Level-3 BLAS on the TI C6678 Multi-core DSP., , , and . SBAC-PAD, page 179-186. IEEE Computer Society, (2012)