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Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board., and . Microelectronics Reliability, 46 (2-4): 301-310 (2006)Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation., and . Microelectronics Reliability, 50 (1): 48-56 (2010)PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit., and . Microelectronics Reliability, 53 (2): 208-214 (2013)ESD protection design for CMOS RF integrated circuits using polysilicon diodes., and . Microelectronics Reliability, 42 (6): 863-872 (2002)Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit., and . Microelectronics Reliability, 54 (1): 64-70 (2014)New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation., and . IEEE Trans. on Circuits and Systems, 53-II (8): 667-671 (2006)Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations., and . IEEE Trans. on Circuits and Systems, 53-I (2): 235-246 (2006)Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process., and . IEICE Transactions, 91-C (3): 378-384 (2008)System-Level ESD Protection Design with On-Chip Transient Detection Circuit., , and . ICECS, page 616-619. IEEE, (2006)CMOS Power Amplifier with ESD Protection Design Merged in Matching Network., , and . ICECS, page 825-828. IEEE, (2007)