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Device-architecture co-optimization of STT-RAM based memory for low power embedded systems., , , , , and . ICCAD, page 463-470. IEEE Computer Society, (2011)Multi retention level STT-RAM cache designs with a dynamic refresh scheme., , , , , , and . MICRO, page 329-338. ACM, (2011)Software testing sizing in incremental development: A case study., , and . ESEM, page 490-493. IEEE Computer Society, (2009)Simulation research on rear active steering-based 4WIS electric vehicle steering control., , , , and . M2VIP, page 1-6. IEEE, (2017)Probabilistically Programmed STT-MRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (1): 42-51 (2012)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors., , , , , and . ICCAD, page 1-8. IEEE, (2013)Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach., , , , , and . IEEE Trans. Multi-Scale Computing Systems, 1 (4): 195-206 (2015)Simulation of the defect removal process with queuing theory., , , and . ESEM, page 473-476. IEEE Computer Society, (2009)A Simulating System for NC Lathe., and . ITAMS, volume B-1 of IFIP Transactions, page 291-297. North-Holland, (1991)An Experience-Based Approach for Test Execution Effort Estimation., , , , and . ICYCS, page 1193-1198. IEEE Computer Society, (2008)