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Logic Synthesis for Engineering Change.

C. Lin, K. Chen, S. Chang, M. Marek-Sadowska, and K. Cheng. DAC, page 647-652. ACM Press, (1995)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yayi Lin University of Stuttgart

Estefania Linuesa Torrijos University of Stuttgart

Robert Lindemann University of Stuttgart

Hendrik Linder University of Stuttgart

Chih-Hao Wang University of Stuttgart

Other publications of authors with the same name

Sequential Permissible Functions and their Application to Circuit Optimization.C. Lin, M. Marek-Sadowska, K. Chen, and M. Lee. ED&TC, page 334-339. IEEE Computer Society, (1996)On designing universal logic blocks and their application to FPGA design.C. Lin, and M. Marek-Sadowska. IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (5): 519-527 (1997)Logic rectification and synthesis for engineering change.C. Lin, D. Cheng, M. Marek-Sadowska, and K. Chen. ASP-DAC, ACM, (1995)Cost-free scan: a low-overhead scan path design methodology.C. Lin, M. Lee, M. Marek-Sadowska, and K. Chen. ICCAD, page 528-533. IEEE Computer Society / ACM, (1995)Test Point Insertion: Scan Paths through Combinational Logic.C. Lin, M. Marek-Sadowska, K. Cheng, and M. Lee. DAC, page 268-273. ACM Press, (1996)Impact of Different Course Contents on Working Memory of Elementary School Students.T. Hsu, F. Lin, C. Chang, and H. Peng. HCI (16), volume 8019 of Lecture Notes in Computer Science, page 316-324. Springer, (2013)A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.P. Pan, and C. Lin. FPGA, page 35-42. ACM, (1998)Logic synthesis for engineering change.C. Lin, K. Chen, and M. Marek-Sadowska. IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (3): 282-292 (1999)Cost-free scan: a low-overhead scan path design.C. Lin, M. Marek-Sadowska, M. Lee, and K. Chen. IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (9): 852-861 (1998)A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.D. Pfaff, S. Moazzeni, L. Gao, M. Chuang, X. Wang, C. Palusa, R. Abbott, R. Ramirez, M. Amer, M. Huang and 5 other author(s). VLSI Circuits, page 270-. IEEE, (2019)

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Disambiguation of "Lin, Chih-Chang"

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Logic Synthesis for Engineering Change.

Please choose a person to relate this publication to

Yayi Lin University of Stuttgart

Estefania Linuesa Torrijos University of Stuttgart

Robert Lindemann University of Stuttgart

Hendrik Linder University of Stuttgart

Chih-Hao Wang University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Lin, Chih-Chang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Logic Synthesis for Engineering Change.

Please choose a person to relate this publication to

Yayi Lin University of Stuttgart

Estefania Linuesa Torrijos University of Stuttgart

Robert Lindemann University of Stuttgart

Hendrik Linder University of Stuttgart

Chih-Hao Wang University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Logic Synthesis for Engineering Change.