Author of the publication

Optimizing the Fast Fourier Transform on a Multi-core Architecture.

, , , and . IPDPS, page 1-8. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks., , and . VLSI Signal Processing, 31 (3): 207-229 (2002)Rate-optimal schedule for multi-rate DSP computations., and . VLSI Signal Processing, 9 (3): 211-232 (1995)Co-Scheduling Hardware and Software Pipelines., , and . HPCA, page 52-61. IEEE Computer Society, (1996)Partial Sampling with Reverse State Reconstruction: A New Technique for Branch Predictor Performance Estimation., and . HPCA, page 342-351. IEEE Computer Society, (1998)Automatically Partitioning Threads Based on Remote Paths., and . ICPADS, page 632-639. IEEE Computer Society, (1998)Analysis of Multithreaded Multiprocessors with Distributed Shared Memory., , , and . SPDP, page 114-121. IEEE Computer Society, (1993)Efficient support of concurrent threads in a hybrid dataflow/von Neumann architecture., and . SPDP, page 190-193. IEEE Computer Society, (1991)On memory models and cache management for shared-memory multiprocessors., and . SPDP, page 190-193. IEEE, (1995)Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study., , , and . ICCD, page 174-179. IEEE Computer Society, (2002)A dynamic schema to increase performance in many-core architectures through percolation operations., , , , , and . HiPC, page 276-285. IEEE Computer Society, (2013)