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Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening.

G. Cabodi, P. Camurati, M. Palena, P. Pasini, and D. Vendraminetto. FMCAD, page 25-32. IEEE, (2016)

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Interpolation sequences revisited.G. Cabodi, S. Nocco, and S. Quer. DATE, page 316-322. IEEE, (2011)Tightening BDD-based approximate reachability with SAT-based clause generalization∗.G. Cabodi, P. Pasini, S. Quer, and D. Vendraminetto. DATE, page 1-6. European Design and Automation Association, (2014)Verification and synthesis of counters based on symbolic techniques.G. Cabodi, P. Camurati, L. Lavagno, and S. Quer. ED&TC, page 176-181. IEEE Computer Society, (1997)Cross-fertilizing FSM verification techniques and sequential diagnosis.G. Cabodi, P. Camurati, F. Corno, P. Prinetto, and M. Reorda. EURO-DAC, page 306-311. IEEE Computer Society Press, (1992)Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking.G. Cabodi, P. Camurati, L. Garcia, M. Murciano, S. Nocco, and S. Quer. FMCAD, page 1-8. IEEE, (2008)Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking.G. Cabodi, M. Crivellari, S. Nocco, and S. Quer. DATE, page 688-689. IEEE Computer Society, (2005)Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking.G. Cabodi, M. Palena, and P. Pasini. FMCAD, page 43-50. IEEE, (2014)Symbolic traversals of data paths with auxiliary variables.G. Cabodi, P. Camurati, and S. Quer. Great Lakes Symposium on VLSI, page 93-96. IEEE, (1994)TPDL: Extended Temporal Profile Description Language.G. Cabodi, P. Camurati, P. Prinetto, and M. Reorda. Softw., Pract. Exper., 21 (4): 355-374 (1991)Improved reachability analysis of large finite state machines.G. Cabodi, P. Camurati, and S. Quer. ICCAD, page 354-360. IEEE Computer Society / ACM, (1996)

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Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening.

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Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening.