Author of the publication

13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

J. Mulder, D. Vecchi, Y. Ke, S. Bozzola, M. Core, N. Saputra, Q. Zhang, J. Riley, H. Yan, M. Introini, S. Wang, C. Ward, J. Westra, J. Wan, and K. Bult. ISSCC, page 1-3. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. rer. pol. Klaas Macha University of Stuttgart

Klaas Pruiksma University of Stuttgart

Dr. -Ing. Norbert Klaas University of Stuttgart

Other publications of authors with the same name

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.J. Westra, J. Mulder, Y. Ke, D. Vecchi, X. Liu, E. Arslan, J. Wan, Q. Zhang, S. Wang, F. van der Goes and 1 other author(s). CICC, page 1-8. IEEE, (2014)A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.C. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, and K. Bult. J. Solid-State Circuits, 44 (12): 3285-3293 (2009)A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration.R. Sehgal, F. van der Goes, and K. Bult. J. Solid-State Circuits, 50 (7): 1592-1603 (2015)An 800MS/s dual-residue pipeline ADC in 40nm CMOS.J. Mulder, F. van der Goes, D. Vecchi, J. Westra, E. Ayranci, C. Ward, J. Wan, and K. Bult. ISSCC, page 184-186. IEEE, (2011)A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS.S. Spiridon, J. van der Tang, H. Yan, H. feng Chen, D. Guermandi, X. Liu, E. Arslan, F. van der Goes, and K. Bult. J. Solid-State Circuits, 48 (7): 1595-1604 (2013)A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.M. Akter, R. Sehgal, F. van der Goes, K. Makinwa, and K. Bult. J. Solid-State Circuits, 53 (10): 2939-2950 (2018)A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.R. Sehgal, F. van der Goes, and K. Bult. ESSCIRC, page 67-70. IEEE, (2014)A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction.M. Akter, R. Sehgal, F. van der Goes, and K. Bult. ESSCIRC, page 315-318. IEEE, (2015)A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers.R. Sehgal, F. van der Goes, and K. Bult. ESSCIRC, page 131-134. IEEE, (2017)26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.J. Mulder, D. Vecchi, Y. Ke, S. Bozzola, M. Core, N. Saputra, Q. Zhang, J. Riley, H. Yan, M. Introini and 5 other author(s). ISSCC, page 1-3. IEEE, (2015)

PUMA

Disambiguation of "Bult, Klaas"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Please choose a person to relate this publication to

Dr. rer. pol. Klaas Macha University of Stuttgart

Klaas Pruiksma University of Stuttgart

Dr. -Ing. Norbert Klaas University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Bult, Klaas"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Please choose a person to relate this publication to

Dr. rer. pol. Klaas Macha University of Stuttgart

Klaas Pruiksma University of Stuttgart

Dr. -Ing. Norbert Klaas University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.