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k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.

K. Townsend, S. Sun, T. Johnson, O. Attia, P. Jones, and J. Zambreno. EIT, page 257-263. IEEE, (2015)

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Dr. Joseph Michaels University of Stuttgart

Other publications of authors with the same name

A project-based embedded systems design course using a reconfigurable SoC platform.D. Roggow, P. Uhing, P. Jones, and J. Zambreno. MSE, page 9-12. IEEE Computer Society, (2015)A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach.X. Wang, P. Jones, and J. Zambreno. ISVLSI, page 541-546. IEEE Computer Society, (2014)A hardware pipeline for accelerating ray traversal algorithms on streaming processors.M. Steffen, and J. Zambreno. SASP, page 22-29. IEEE Computer Society, (2010)Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications.M. Awatramani, X. Zhu, J. Zambreno, and D. Rover. PACT, page 1-12. IEEE Computer Society, (2015)An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System.A. Das, S. Misra, S. Joshi, J. Zambreno, G. Memik, and A. Choudhary. DATE, page 1160-1165. ACM, (2008)Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.M. Qasaimeh, K. Denolf, J. Lo, K. Vissers, J. Zambreno, and P. Jones. ICESS, page 1-8. IEEE, (2019)Work-in-Progress: Real-Time Modeling for Intrusion Detection in Automotive Controller Area Network.H. Olufowobi, G. Bloom, C. Young, and J. Zambreno. RTSS, page 161-164. IEEE Computer Society, (2018)Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection.X. Zhu, R. Wernsman, and J. Zambreno. ICPP, page 64:1-64:10. ACM, (2018)An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition.X. Wang, and J. Zambreno. IPDPS Workshops, page 220-227. IEEE Computer Society, (2014)Mining Association Rules with systolic trees.S. Sun, and J. Zambreno. FPL, page 143-148. IEEE, (2008)

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Disambiguation of "Zambreno, Joseph"

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k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.

Please choose a person to relate this publication to

Dr. Joseph Michaels University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Zambreno, Joseph"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.

Please choose a person to relate this publication to

Dr. Joseph Michaels University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
DIN 1505
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k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.