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Disambiguation of "Li, Qing'an"

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Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory.

, , , , , , , and . IEEE Trans. VLSI Syst., 21 (7): 1271-1284 (2013)

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M.Sc. Yunxuan Li University of Stuttgart

Yu Li University of Stuttgart

Zheng Li University of Stuttgart

Jie Li University of Stuttgart

Li Zhong University of Stuttgart

 

Other publications of authors with the same name

Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (3): 329-342 (2014)Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache., , , , and . ISVLSI, page 410-415. IEEE Computer Society, (2012)Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems., , and . TrustCom, page 1038-1044. IEEE Computer Society, (2011)Integer Promotion Elimination on Abstract Syntax Tree., , , , and . CIT, page 2367-2372. IEEE Computer Society, (2010)Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM., , and . DAC, page 106:1-106:6. ACM, (2014)Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache., , , , , and . IEEE Trans. Computers, 64 (8): 2169-2181 (2015)Memory-aware TLP throttling and cache bypassing for GPUs., , , , and . Cluster Computing, 22 (Suppl 1): 871-883 (2019)Compiler directed automatic stack trimming for efficient non-volatile processors., , , , , and . DAC, page 183:1-183:6. ACM, (2015)WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture., , , , and . IEEE Trans. VLSI Syst., 22 (1): 168-180 (2014)Cache coherence enabled adaptive refresh for volatile STT-RAM., , , , , and . DATE, page 1247-1250. EDA Consortium San Jose, CA, USA / ACM DL, (2013)