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A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (1): 121-131 (2012)

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Energy Optimization for Latency- and Quality-Constrained Video Applications., and . IEEE Design & Test of Computers, 21 (5): 358-366 (2004)Software synthesis for dynamic data flow graph., and . IEEE International Workshop on Rapid System Prototyping, page 72-79. IEEE Computer Society, (1997)Software synthesis in the ESL methodology for multicore embedded systems., and . ICSAMOS, page 355-362. IEEE, (2011)A Hybrid Performance Analysis Technique for Distributed Real-Time Embedded Systems., , and . CoRR, (2016)Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach., , , , , and . ACM Trans. Embedded Comput. Syst., 13 (4s): 135:1-135:26 (2014)An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems., , , , , and . RTSS, page 363-372. IEEE Computer Society, (2012)Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing., , and . ICPP, page 122-127. IEEE Computer Society, (1997)Pipelined data parallel task mapping/scheduling technique for MPSoC., and . DATE, page 69-74. IEEE, (2009)Optimized Timed Hardware Software Cosimulation without Roll-back., and . DATE, page 945-946. IEEE Computer Society, (1998)A Hardware Software Cosimulation Backplane with Automatic Interface Generation., and . ASP-DAC, page 177-182. IEEE, (1998)