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A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillators.

, , , , , , and . SoCC, page 7-10. IEEE, (2007)

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A pixel array PSD with divide-by-M winner-take-all architecture., and . IEICE Electronic Express, 4 (3): 82-87 (2007)A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver., , and . IEEE Trans. on Circuits and Systems, 52-II (7): 389-393 (2005)A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF., , and . IEEE Trans. on Circuits and Systems, 62-I (1): 80-89 (2015)Code-width testing-based compact ADC BIST circuit., , , , and . IEEE Trans. on Circuits and Systems, 51-II (11): 603-606 (2004)A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture., , , , , , , , and . J. Solid-State Circuits, 46 (1): 236-247 (2011)A Low Power Dual-Mode Sigma-Delta Modulator for GSM/WCDMA Receivers., , and . ICECS, page 1151-1154. IEEE, (2007)A 0.8-µW switched-capacitor sigma-delta modulator using a class-C inverter., , and . ISCAS (1), page 1152-1155. IEEE, (2004)An adaptation method for FIR pre-emphasis filter on backplane channel., and . ISCAS, IEEE, (2006)An Acceleration Processor for Data Intensive Scientific Computing., , , , and . IEICE Transactions, 87-D (7): 1766-1773 (2004)Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator., and . J. Solid-State Circuits, 44 (2): 458-472 (2009)